In recent times, the testing input/output (I/O) circuitry on front-side bus (FSB) based microprocessor products was possible using conventional testers. This is because the FSB speed was comparable to the actual tester speeds. For example, in the context of testing an analog interface, a manufacturer could simply buy different testers having a desired frequency. However, as the speed of FSB I/O ports increased dramatically, new protocols needed to be developed to accommodate these scenarios. The alternating current I/O loop back (ACIOLB) test technique was used to test the I/O circuitry with on-die interconnect built-in self-test (IBIST) circuitry. With the advent of 3G I/O circuitry, the challenge of testing I/O circuitry further increased. 3G I/O circuits operate at speeds of 2.5 Gbs and the voltage swings can be in the order of millivolts (i.e., a fraction of the I/O power supply voltage). Testing 3G I/O circuitry using slow testers was possible by implementing I/O Design For Test (DFT) features (e.g., on-die loop back IBIST logic). Moreover, it has become impossible to keep up with the rapidly changing I/O frequencies. In essence, it has become futile to continue chasing high-end frequency testers in hopes of offering suitable testing solutions for various electronic products.
The FIGURES of the drawings are not necessarily drawn to scale or proportion, as their dimensions, arrangements, and specifications can be varied considerably without departing from the scope of the present disclosure.